Introduction to IC Design Tsung-Chu Huang (黃宗柱) Department of Electronic Eng. Chong Chou Institute of Tech. Email: tch@dragon.ccut.edu.tw 2003/11/03

Outline CMOS Logic Gate Design Standard Cell Layout Gate Array Layout Sea of Gates CMOS Layout Guideline Transmission Gate Layout MUX Layout CMOS Logic Structures Clocking Strategies I/O Structures Low-Power Design

To that nearest to output in the serial transistors Fan-In and Fan-Out A D Fanin=3 Fanout=4 A D To that nearest to output in the serial transistors

CMOS Gate Stage-Ratio Principle (Review) IO PAD

Transistor Stage-Ratio Principle 1 ↓ CDS OCg s:1 Rp/s rOCg output part internal part

Transistor Stage-Ratio Principle Equal Rise/Fall Time Design Normalized-mobility

Transistor Stage-Ratio Principle High-Speed Design Guideline Use NAND instead of NOR gates Place inverters at high-fanout nodes Fanin < 5; Fanout < 10 Use min.-sized gates on high-fanout nodes; Keep Rise/Fall edges sharp

Complex Logic Gate Layout Euler Path (Review)

CMOS(互補金氧半) Logic P型網路為F(X)的Relay logic N型網路為F(X)的Relay logic P型網路 F X AND與OR互換即可 N型網路為F(X)的Relay logic

Stick Diagram 常用佈局表示法及簡化佈局法 例： 格子(Grid)狀文字(Font)表示法 EDIF 為一種(層次，對角座標)的表示法 Stick diagram: 草圖用，將不重要寬度省略 例： 2/0.35 1/0.35

例如：F=(A+B)(C+D) A B C D A B C D 因為F= A B + C D P型網路為： 因為F=(A+B)(C+D) A N型網路為：

尤拉路徑 (Euler Path) 十八世紀拓樸學被用來簡化CMOS邏輯閘佈局 N型路徑為N型Relay-logic網路 P型路徑為P型Relay-logic網路 拓樸學證明各輸入開關X與X交叉通過！ B A F S F D

尤拉路徑 (Euler Path)佈局法 再畫出兩倍寬度的P+IMP 先畫出一倍寬度的N+IMP A B VDD B A F S D A B VSS

Interlaces of Diffusion Lines B C D E A B C E D Vdd Out Vss Out A B E D C A B E D C

Minimum Interlace Algorithm Example: A B C D E F Out Out Vss F E D C A B Out Vdd

Minimum Interlace Algorithm Adding a pseudo input to each sub-gate such that each sub-gate has odd inputs. A B C D E F 2 interlaces

Minimum Interlace Algorithm Rotate each axis to reduce the inner interlaces A B C D E F

Output Capacitance Minimization B C D COA COBCD COBCD >> COA Put Output-point here because

Stacking along Diffusion Lines Example: considering a buffer with a stage ratio of 2 Area: A2 1:2 Area: A1 Ln1+Ln2 Wn1+Wn2 Area: A3 Vinv↗

Channel Routing I H A B B C C A D F D To reduce #Tracks E G I B A G F

LEA: Left-Edge Algorithm Sort by length Select from Left Edge A B C D F G E Length Edge

Rapid Prototyping Prototyping: Q<<Qproduct for test, debug, verification. Rapid Prototyping: t(Q) << t(Qproduct) Usual Rapid Prototyping wrt. Full Custom Semi-Custom: saving the prior processes Weinberger Array, Gate Array, SOG, e.t.c. Standard-Cell: saving PLD SPLD CPLD FPGA

Weinberger Array (NOR Logic) D E F G

Gate Matrix

Gate Array

SOG: Sea-of-Gates

Physical Layout Skills Widening methods: Crossover:

Physical Layout Skills Dog-bone/Dog-Leg: No need to change layers for crossing More usage of white space: Rubber forcing

Folding Lines of Diffusion Example: Full Adder

Folding Lines of Diffusion Example: Full Adder A B C Co Co Sum

Folding Lines of Diffusion Example: Sum=A⊕B⊕C A B B A C C A B F Y V F Y V S X F S X F

Connections of Standard Cells 1. Butting 1. Wired 3. Feedthrough

Transmission Gate Layout Consideration

Multiplex A B C Z 1 A B C A B

Multiplex Layout A B

Pass-Transistor and Transmission Gate High-Z or Vth-Degrade PASS Transistor Logic Circuit Pull-up or Pull-down PASS Transistor Logic Circuit A B

Address Decoder using Pass Transistor

4-Transistor XOR and XNOR B Bui et al. New 4-Transistor XOR and XNOR Designs, AP-ASIC2000.

Scope & Review on the Midterm Lectures from 9/22~11/3. Stick diagram, inv(ENM, ERF, Stage) Multiple choice on common guidelines SPICE Netlist and 3 Major Analyses