PACS IIDR 01/02 Mar 2001 CNR-IFSI1 DPU Subsystem Presentation Renato Orfei CNR-IFSI.

Presentación del tema: "PACS IIDR 01/02 Mar 2001 CNR-IFSI1 DPU Subsystem Presentation Renato Orfei CNR-IFSI."— Transcripción de la presentación:

1 PACS IIDR 01/02 Mar 2001 CNR-IFSI1 DPU Subsystem Presentation Renato Orfei CNR-IFSI

2 PACS IIDR 01/02 Mar 2001 CNR-IFSI2 General Block Diagram DPU-OM SPU-NOM S/C MEC 2 MECH-CONTRO 2 LWL DETECTOR CONTROL PACS S/S SWL DET. GRATING ASS. CHOPPER ASS. FLIP MIRROR ASS. LWL DET. MEC 1 MECH-CONTROL1 SWL DETECTOR CONTROL DPU-REDSPU-RED

3 PACS IIDR 01/02 Mar 2001 CNR-IFSI3 FPGA State Machine ONE Serial I/F To/From DEC/MEC 512 Kw 2 MB 262 Kw 1 MB 5.4 Kw 32 KB 512 Kw 3 MB Data area 32 bit words Program area 48 bit words ICU TSC 21020 DSP Data RAM EEPROM Inst. Program Program RAM Instr. Program From EEPROM S/C TWO Serial I/F To/From SPU PROM Kernel Telemetry upload SW DPU General Block Diagram

4 PACS IIDR 01/02 Mar 2001 CNR-IFSI4 DPU High level block diagram

5 PACS IIDR 01/02 Mar 2001 CNR-IFSI5 CPU Block Diagram

6 PACS IIDR 01/02 Mar 2001 CNR-IFSI6 DC/DC Converter Block Diagram

7 PACS IIDR 01/02 Mar 2001 CNR-IFSI7

8 PACS IIDR 01/02 Mar 2001 CNR-IFSI8

9 PACS IIDR 01/02 Mar 2001 CNR-IFSI9 DPU Mass breakdown Components of the mass breakdown: BOX (240x258x194 mm^3, thickness 3 mm, 2.7 g/cm^3): Baseplate 240x258x3= > 501.5 g Front wall: 240x194x3=>377.1 g Front wall connectors (delta:E)=>150 g Bak wall: 240x194x3=>377.1 g Lateral walls: 258x194x3x2=>754.3 g Cover: 240x258x3=>501.5 g Total Box weight: 2661.5 g CPU boards: 2x 600 g => 1200 g P/L I/F Boards: 2x 480 g => 960 g DC/DC boards: 1000 g => 1000 g Motherboard: 400 g => 400 g Screws etc.: 100 g => 100 g Cabling: 300 g => 300 g Total estimated weight: 6621.5 g (+ - 10 %)

10 PACS IIDR 01/02 Mar 2001 CNR-IFSI10 CDMS COMMUNICATION I/F

11 PACS IIDR 01/02 Mar 2001 CNR-IFSI11 28 V lines S/C operated plus synchronization from S/C to PACS: POWER SUPPLY I/F One I/F for DPU DC/DC converter Other I/Fs for SPU and DEC/MEC controlled by DPU via “Event Pkt” CPU CDMS Event Pkt S/CDPU 28V switches DC/DC SPU & DEC/MEC

12 PACS IIDR 01/02 Mar 2001 CNR-IFSI12 Subsystems Interfaces All HW interfaces implemented with balanced drivers and receivers (LVDS) 3 high speed serial bi-directional links for science data and HK collection: - 2 links to/from SPU -1 link to/from DEC/MEC The links will be used for subsystems commanding and reception of science and HK data

13 PACS IIDR 01/02 Mar 2001 CNR-IFSI13 S/C Interface Block diagram

14 PACS IIDR 01/02 Mar 2001 CNR-IFSI14

15 PACS IIDR 01/02 Mar 2001 CNR-IFSI15

16 PACS IIDR 01/02 Mar 2001 CNR-IFSI16