Arquitectura de Computadores I

Presentación del tema: "Arquitectura de Computadores I"— Transcripción de la presentación:

1 Arquitectura de Computadores I
Memoria Cache

2 Memoria Cache Memoria Principal Memoria Cache

3 Principio de Localidad
Localidad Temporal: Si un dato es buscado, este tiende a ser buscado nuevamente. Localidad Espacial: Si un dato es buscado, datos cercanos tienden a ser buscados.

4 Jerarquía de Memoria Registros Cache Principal Secundaria (Disco)

5 Memoria Cache

6 Jerarquía de Memoria

7 Memoria Cache Unidad mínima de información (Bloque) Nivel alto
Jerarquía de dos niveles Miss: dato pedido por el procesador NO está en el nivel más alto Hit: dato pedido por el procesador SI está en el nivel más alto

8 Memoria Cache Razón de Acierto: Tasa de referencias a memoria que producen aciertos. Razón de Desacierto: 1 - (Razón de Acierto). Tiempo de Acierto: Tiempo que tarda en leer un dato del cache. Penalidad de Desacierto: (Tiempo en Reemplazar Bloque) + (Tiempo de Lectura de Dato al Procesador). Tiempo de Acceso Promedio a Memoria: (Razón de Acierto) * (Tiempo de Acierto) + (Razón de Desacierto) * (Penalidad de Desacierto).

9 Memoria Cache Correspondencia Directa (Direct Mapped)
Completamente Asociativa (Fully Associative) Asociativa por Conjuntos (Set Associative)

10 Correspondencia Directa (Direct Mapped)
Memoria Cache Correspondencia Directa (Direct Mapped)

11 Memoria Cache Dirección del bloque Etiqueta Cache vacía Bit de Validez
Referencia a Memoria Bloque

12 Memoria Cache Referencia a Memoria 1 1 0 1 0

13 Memoria Cache

14 Memoria Cache

15 Notas de Memoria Cache Intel Corp.'s Pentium III processor has 32KB of L1 cache on the processor chip and either 256KB of L2 on-chip or 512KB of L2 off-chip. The L2 cache on the CPU chip can be accessed four times faster than if it were on a separate chip.

16 Notas de Memoria Cache For high-end processors, it can take from one to three clock cycles to fetch information from L1, while the CPU waits and does nothing. It takes six to 12 cycles to get data from an L2 on the processor chip, and dozens or even hundreds of cycles for off-CPU L2.

17 Notas de Memoria Cache Where's my data? When the CPU needs data, it first looks in its own data registers. If the data isn't there, the CPU looks to see if it's in the nearby Level 1 cache. If that fails, it's off to the Level 2 cache. If it's nowhere in cache, the CPU looks in main memory. Not there? The CPU gets it from disk. All the while, the clock is ticking, and the CPU is sitting there waiting.

18 Notas de Memoria Cache In 2000, Intel introduced Level 3 (L3) cache in its 64-bit server processors, called Itanium. The 2MB or 4MB cache connected to the processor over a bus that runs as fast as the processor MHz.

19 Notas de Memoria Cache The frequency of cache misses can be reduced by making caches bigger. But big caches draw a lot of power, generate a lot of heat and reduce the yield of good chips in manufacturing.

20 Notas de Memoria Cache Intel's first Celeron processor has no cache, but the company gave the Celeron A 128K of internal cache. The Pentium II separates the cache from the main chip but keeps it on the board. This is a disadvantage because the PII cache runs at one-half the processor speed. This is why the Celeron A processor can be faster than a PII, even with less cache. The AMD K62 has 64K L1 cache.