Computer Architecture Notes Jan 26, 2004 Dusan Kuzmanovic Jimmy Ortegon
op LOAD Machine Instruction Encoding a A
Three Address Format op ALU CPU MEMORY ADD,,
Two Address Format op ALU CPU MEMORY LOAD R1, ADD, ADD R1, R2 ADD,
One Address Format op 30 ALU CPU MEMORY ADD A
op ADD, Register to Register Format 2 Register R1R2 First Operand Second Operand ADD,, 3 Register Result Second Operand opR1R2R3 First Operand
ALU STACKSTACK SP ADD 1 ALU IR + MEMORY An stack memory SP= Stack Memory Zero Address Architecture – or Stack Architecture
STACK PUSH A ADD POP C ACUMMULATOR LOAD A ADD B STORE C REGISTER MEMORY LOAD R1,A ADD R2,R1,B STORE R3, C LOAD R1,A LOAD R2,B ADD R3,R2,R1 STORE R3 LOAD/ STORE
INTEL PENTIUM 2 ADDRESS FORMAT WITH OPERAND IN A REGISTER AND THE OTHER IN A REGISTER ON MEMORY Sun –Sparc Load/ Store Architecture
MAR PC MDR 1 ALU A IM DM M DECODER ADDROP DM = Data Memory IM = Instruction Memory Harvard Architecture Mark-I First Machine
Parallel Instruction Execution CONDITION CODES MAR 1 IM MDR 1MDR 2 DM MAR 2 PC DECODER ADDROP MULTIPLEXER ALU 1 … OV ><= A
Fetch MAR1 PC MDR 1 IM[MAR1] || PC PC + 1 IR MDR 1 DECODER IR.OP NOTE: JMP depending on PC IR.ADDR
Load MAR 2 IR.ADDR MDR 2 DM[MAR 2] A MDR 2
Add MAR2 IR.ADDR || MAR 1 PC MDR2 DM[MAR 2] || MDR IM[MAR 1] A A + MDR 2 || IR MDR 1