 Seattle Pacific University EE Logic System DesignFSM-1 Elevator Controller We’re hired to design a digital elevator controller for a four-floor.

Presentación del tema: " Seattle Pacific University EE Logic System DesignFSM-1 Elevator Controller We’re hired to design a digital elevator controller for a four-floor."— Transcripción de la presentación:

1  Seattle Pacific University EE 1210 - Logic System DesignFSM-1 Elevator Controller We’re hired to design a digital elevator controller for a four-floor building 00 01 10 11 1st try: Design a counter that counts up and down 00, 01, 10, 11, 10, 01, 00,... Problem: Never stops! 2nd try: Add “Stop” button that disables counter Problem: Have to press button when elevator happens by We need a way to have user inputs into a complex system

2  Seattle Pacific University EE 1210 - Logic System DesignFSM-2 Finite State Machines Counters - Next state based on current state If counter is in state ‘101’, next state is ‘110’ No inputs (other than reset, enable) Finite State Machines Next state is a function of the current state and the inputs If the elevator is on floor 00 and the UP button is pressed on floor 10, then move to floor 01 If current state is 00  If UP2, Next state is 01

3  Seattle Pacific University EE 1210 - Logic System DesignFSM-3 A Finite State Machine Combinational Logic For Next State Comb. Logic For Outputs State FlipFlops Clock Current State Next State Inputs Elevator Buttons Motor/Door Controls Current floor/ direction Next floor/ direction Example shown for elevator controller

4  Seattle Pacific University EE 1210 - Logic System DesignFSM-4 Gumball Machine We’re building a gumball machine 15 cents for a gumball Machine has a single slot, which can take dimes or nickels Subcontractor provides a coin sensor, which has two outputs: N is true if a nickel was input D is true if a dime was input We must provide the output Open when 15 cents entered Gumball Machine FSM N D Reset Clk Open Coin Sensor Candy Release Mechanism

5  Seattle Pacific University EE 1210 - Logic System DesignFSM-5 Gumball Machine Tabulate typical input sequences: three nickels nickel, dime two nickels, dime two dimes dime, nickel Draw state diagram: Inputs: N, D, reset Output: open Diagram what is going on in a state diagram S0S1S2S3 [open=1] S4 [open=1] S5 [open=1] S6 [open=1] S8 [open=1] S7 D D D D N N N N Reset Output (open) indicated during states in which is is asserted Note: No change provided! N’D’N’D’ S0 N S1 D S2 N’D’N’D’ S0 N S1 D S2 N’D’N’D’ S0 N S1 D S2 N’D’N’D’ S0 N S1 D S2 N’D’N’D’ S0 N S1 D S2 N’D’N’D’ N’D’N’D’ N’D’N’D’ N’D’N’D’

6  Seattle Pacific University EE 1210 - Logic System DesignFSM-6 A More Efficient Solution Reuse states whenever possible Symbolic State Table 0¢ 5¢ 10¢ D D N N N+DN+D Reset 15 + ¢ [open=1] 15 + ¢ 0¢0¢ 5¢5¢ 10¢ X 15 + ¢ 10¢ 5¢5¢ X X 5¢5¢ X 0¢0¢ Q Current State Open Output 0¢0¢0 5¢5¢0 10¢0 15 + ¢1 0010¢ 10 01 115¢5¢ 11 0015 + ¢ 10 01 11 015¢5¢ 105¢5¢ 005¢5¢ 110¢0¢ 010¢0¢ 100¢0¢ 000¢0¢ Q+ Next State N Input D Input Q Current State Output Table N’D’N’D’ N’D’N’D’ N’D’N’D’ N’D’N’D’ D N

7  Seattle Pacific University EE 1210 - Logic System DesignFSM-7 Gumball Machine State Table Encode states into binary numbers Calculate total number of states: 4 (0 ¢, 5 ¢, 10 ¢, 15 ¢ ) Use as many bits as needed for the states 4 states --> 2 bits Encoding:0 ¢: 00 5 ¢ :01 10 ¢ :10 15 + ¢ :11 Calculate total number of states: 4 (0 ¢, 5 ¢, 10 ¢, 15 ¢ ) Use as many bits as needed for the states 4 states --> 2 bits Encoding:0 ¢: 00 5 ¢ :01 10 ¢ :10 15 + ¢ :11 Encoded State Table X 1 0 0 X 1 1 1 X 1 1 0 X 1 0 0 0 1 1 X X 0 1 0 X 1 0 1 X 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 0 0 0 0 Q 1 Q 0 Current State 00 10 01 11 11 00 10 01 11 01 10 00 11 01 10 00 Q 1 + Q 0 + Next State N Input D Input Q 1 Q 0 Current State Open Output 0 0 0 010 1 0 0 111 Output Table

8  Seattle Pacific University EE 1210 - Logic System DesignFSM-8 Gumball Machine Implementation Q1Q0Q1Q0 DN 00011110 00 01 11 10 Q1Q1 Q0Q0 D N D1D1 1 0 x 1x0 0 1 1 x 1 01 0x 1 Q1Q0Q1Q0 DN 00011110 00 01 11 10 Q1Q1 Q0Q0 D N D0D0 1 1 x 0x0 0 1 0 x 1 10 1x 0 D 1 = D + NQ 0 Q 1 ’ + Q 0 ’Q 1 D 2 = NQ 0 ’ + N’Q 1 ’Q 0 + NQ 1 + DQ 1 Q 0 ’ Open = Q 1 Q 0 Note that the output is a function of only the state If we chose D FF’s, we don’t have to convert Q’s to FF inputs Q 1 Q 0 Current State Open Output 0 0 0 010 1 0 0 111

9  Seattle Pacific University EE 1210 - Logic System DesignFSM-9 Inputs FSMs change state based on clock edges I.e. Rising clock edge clocks all FFs This part can change only when clock “ticks” Combinational Logic For Next State Comb. Logic For Outputs State FlipFlops Clock Inputs This part can change at any time Synchronous Inputs: Change in synch with the clock. Obey setup and hold time. Asynchronous Inputs: Change at any time. May violate setup and hold times.

10  Seattle Pacific University EE 1210 - Logic System DesignFSM-10 Asynchronous vs. Synchronous Inputs Asynchronous Synchronous Example: Elevator pushbuttons Arrive at any time Usually asserted for many clock cycles FSM logic must not make any assumptions about input timing Example: Data arriving on a serial line from a computer Arrive synchronized exactly to a clock One bit of data per clock cycle FSM can assume that data changes once per clock cycle

11  Seattle Pacific University EE 1210 - Logic System DesignFSM-11 Parity Checker Assert output (parity) whenever input bit stream (synchronous) has odd # of 1's Q Present State In Input Q+ Next State Even00 0 01Odd1 10 1 11Even0 State Diagram Even [0] Odd [1] Reset In In’ Q Present State Parity Output Even00 Odd11 Q+ = Q  In Parity = Q

12  Seattle Pacific University EE 1210 - Logic System DesignFSM-12 Parity Checker Parity Checking is a type of Synchronous Serial Input FSM A single input Input is synchronized with clock (1 bit per clock cycle) Goal is to look for patterns in the input bit stream D FF Implementation T FF Implementation DQ Clr Parity In Reset TQ Pre Clr Parity In Reset Q+ = Q  In Parity = Q

13  Seattle Pacific University EE 1210 - Logic System DesignFSM-13 Pattern Matcher A string recognizer has one synchronous input (X) and one output (Z). The output is asserted whenever the input sequence …010… has been observed, as long as the sequence …100… has never been seen. Sample input/output behavior: 00010000000Z: 01001011011X: 00010101000Z: 01001010100X: This is a synchronous serial input problem 1. Work though sample inputs to understand problem 2. Develop FSM to recognize patterns 3. Implement using standard techniques

14  Seattle Pacific University EE 1210 - Logic System DesignFSM-14 Pattern Matcher 1.Pick a reset state. 2.Draw paths for strings to recognize (010 and 100) 3.Fill in all of the missing transitions (each state needs a path out for 0 and 1) Reset signal places FSM in S0 Outputs 1 Loops in State S0 [0] S1 [0] S2 [0] S3 [1] S4 [0] S5 [0] S6 [0] 0+1 Reset 1 00 0 0 1...010...100 State S3: have recognized …010 if next input is 0 then have …0100 (state S6) if next input is 1 then have …0101 = …01 (state S2) 0 1 State S1: recognizes strings of form …0 (no 1 seen) loop back to S1 if input is 0...01 State S4: recognizes strings of form …1 (no 0 seen) loop back to S4 if input is 1...0 0...1 1 State S2: if input is 1, then have …1 (state S4) State S5: recognizes …10 if input is 1, then have …01 (state S2)...10 1 1

15  Seattle Pacific University EE 1210 - Logic System DesignFSM-15 Pattern Matcher - Implementation 1.Assign each state a binary number 2.Make the state transition table 3.Make the output table S0 [0] S1 [0] S2 [0] S3 [1] S4 [0] S5 [0] S6 [0] 0+1 Reset 1 00 0 0 1 0 1 0 1 1 1 Current StateInputNext State Q2Q2 Q1Q1 Q0Q0 XQ2Q2 Q1Q1 Q0Q0 0000001 0001100 0010001 0011010 0100011 0101100 0110110 0111010 1000101 1001100 1010110 1011010 1100110 1101110 1110XXX 1111XXX 000 001 010 011 110 101 100

16  Seattle Pacific University EE 1210 - Logic System DesignFSM-16 Pattern Matcher - Implementation 1.Assign each state a binary number 2.Make the state transition table 3.Make the output table Current StateOutput Q2Q2 Q1Q1 Q0Q0 Z 0000 0010 0100 0111 1000 1010 1100 111X S0 [0] S1 [0] S2 [0] S3 [1] S4 [0] S5 [0] S6 [0] 0+1 Reset 1 00 0 0 1 0 1 0 1 1 1 000 001 010 011 110 101 100 Build the FSM: Use three FF’s Build next state logic based on state transition table Build output logic based on output table