Memorias.

Presentación del tema: "Memorias."— Transcripción de la presentación:

1 Memorias

2 Memorias en General Un simple flip-flop es un elemento básico de memoria En general el termino memoria se usa para un arreglo bidimensional, en el cual se puede acceder a una fila de bits en un cierto tiempo Memorias son CI usados con otros CI (microprocesadores, MEF, contadores, etc) En un sistema basado en microprocesador una memoria se usa para almacenar las instrucciones a ser ejecutadas por el microprocesador, y también para almacenar los datos a procesar o procesados Otros usos incluye almacenamiento de audio en un DVD player por ejemplo, voces digitales, mensajes de LEDs, etc, latch the ny sequential word stores "memor one circuit bit y"of to has information. refer memory to bits ofthat Ho a sort, ware ever, since stored weeach uin sually aflip-flop struc reserve tured or way, usually as a two-dimensional array in which one row of bits is accessed at a time. This chapter describes several different types of memory organizations and commercially available memory chips. The same kinds of memory may be embedded into larger VLSI chips, where they are combined with other circuits to perform a useful function. The applications of memory are many and varied. In a microprocessor's central processing unit (CPU), a "read-only memory" may be used to define multiple small steps used to execute each complex instruction in the CPU's instruction set, or to store "seed" constants used in a division algorithm. Alongside the CPU, a fast "static memory" may serve as a cache to hold recently used instructions and data. And a microprocessor's mainmemory subsystem may contain billions of bits in "dynamic memory" that store complete operating systems, programs, and data. Applications of memory are not limited to microprocessors or even to purely digital systems. For example, equipment in the public telephone system uses read-only memories to perform certain transformations on digitized voice signals, and fast "static memories" as a "switching fabric" to route digitized voice between subscribers. Most portable audio compact- disc players "read ahead" and store several seconds of audio in a "dynamic memory" so that the unit can keep playing even if it is physically jan-ed (this requires over 1.4 million bits per second of stored audio). And there are many examples of modern audio/visual equipment that use memories to temponuily store digitized signals for enhancement through digital signal processing. ICTP FPGA-VHDL

3 Memorias en General ICTP FPGA-VHDL

4 Memoria de Solo Lectura (ROM)
Las memorias de solo lectura son conocidas por la siglas ROM, que en inglés significa Read Only Memory Las memorias ROM almacenan cierta información, que se graba originalmente por algún medio, y esa información, al ser la memoria de solo lectura, no se puede modificar ICTP FPGA-VHDL

5 Memoria ROM Desde el punto de vista de un sistema digital una ROM puede ser definida como un sistema combinacional con n entradas y b salidas A read-only memory (ROM) is a combinational circuit with n inputs and b outputs, as shown in Figure 9-1. The inputs are called address inputs and are traditionally named AO, A1, ... , An-1. The outputs are called data outputs and are typically named DO, 01 , ... , Db-1. Las entradas son llamadas ‘direcciones de entradas’, y tradicionalmente se las identifica con la letra A (de address), y un número: A0, A1, .. etc Las salidas son llamadas ‘datos de salida’, y tradicionalmente se las identifica con la letra D (de data), y un número: D0, D1, .. Etc. ICTP FPGA-VHDL

6 Memorias ROM Una ROM almacena la tabla de verdad una función combinacional de n-inputs y b-outputs ROM A2 D3 A1 D2 D1 A ROM "stores" the truth table of an n-input, b-output combinational logic function. For example, Table 9-1 is the truth table of a 3-input, 4-output combinational function; it could be stored in a 23 x 4 (8 x 4) ROM. Neglecting propagation delays, a ROM's data outputs at all times equal the output bits in the truth-table row selected by the address inputs. A0 D0 ROM 8 x 4 (23 x 4) ICTP FPGA-VHDL

7 Memorias ROM Using ROMs for "Random" Combinational Logic Functions Table 9-1 is actually the truth table of a 2-to-4 decoder with an output-polarity control, a function that can be built with discrete gates as shown in Figure 9-2. Thus, there are at least two different ways to build the decoder-with discrete gates, or with an 8 x 4 ROM that contains the truth table, as shown in Figure 9-3. The assignment pattern of decoder inputs and outputs to ROM inputs and outputs in Figure 9-3 is a consequence of the way that the truth table in Table 9-1 is constructed. Thus, the physical ROM realization of the decoder is not unique. ICTP FPGA-VHDL

8 Memoria ROM Las memorias ROM tienen una particularidad que las hacen muy útiles: son memorias NO VOLÁTILES Although we think of ROM as being a type of memory, it has an important difference from most other types of integrated-circuit memory. ROM is nonvolatile memory; that is, its contents are preserved even if no power is applied. ICTP FPGA-VHDL

9 Memorias ROM Cuando se usa una ROM para almacenar una tabla de verdad, las entradas de la tabla de verdad se ordenan de izquierda a derecha, siendo la primer entrada de la izquierda el valor mas significativo del arreglo de entradas Del mismo modo las salidas de la tabla de verdad se ordenan de izquierda a derecha, siendo la primer salida de la izquierda el valor mas significativo del arreglo de salidas When constructing a ROM to store a given truth table, input and output signals reading from right to left in the truth table are normally assigned to ROM address inputs and data outputs with ascending labels. Each address or data combination may then be read as a corresponding binary integer with the bits numbered in the "natural" way. A data file is typically used to specify the truth table to be stored in the ROM when it is manufactured or programmed. The data file usually gives the address and data values as hexadecimal numbers. For example, a data file may specify Table 9-2 by saying that ROM addresses 0-7 should store the values E, 1, D, 2, B, 4, 7, 8. Tanto las direcciones como los datos de una ROM se escriben en Hexadecimal ICTP FPGA-VHDL

10 Ejemplo de Uso de ROM: Multiplicador 4x4
Another simple example of a function that can be built with ROM is 4 x 4 unsigned binary multiplication. We showed an ABEL program for this function in Section and found that the number of product terms required (36) was too high to obtain with just one pass through a conventional PLD's AND-OR array. Alternatively, we can realize the function with one pass through a 28 x 8 (256 x 8) ROM with the connections shown in Figure 9-4. A ROM's contents are normally specified by a file that contains one entry for every address in the ROM. For example, Table 9-3 is a hexadecimal listing of the 4 x 4 multiplier ROM contents. Each row gives a starting address in the ROM and specifies the 8-bit data values stored at 16 successive addresses. The nice thing about ROM-based design is that you can usually write a simple program in a high-level language to calculate what should be stored in the ROM. For example, it took only a few minutes to write a C program, shown in Table 9-4, that generated the contents of Table 9-3 ICTP FPGA-VHDL

11 Estructura Interna de una ROM
Cada fila del decodificador es llamada línea de palabra Cada línea vertical es llamada línea de bit The mechanism used by ROMs to "store" information varies with different ROM technologies. In most ROMs, the presence or absence of a diode or transistor distinguishes between a Oand a 1. Figure 9-5 is the schematic of a primitive 8 x 4 ROM that you could build yourself usi ng an MSI decoder and a handful of diodes. The address inputs select one of the decoder outputs to be asserted. Each decoder output is called a word line because it selects one row or word of the table stored in the ROM. The figure shows the situation with A2-AO = 10l and ROW5_L asserted. Each vertical line in Figure 9-5 is called a bit line because it corresponds to one output bit of the ROM . An asserted word line pulls a bit line LOW if a diode is connected between the word line and the bit line. There is only one diode in row 5, and the corresponding bit line (D1_L) is pulled LOW. The bit lines are buffered through inverters to produce the D3-DO ROM outputs, 0010 for the case shown. In the ROM circuit of Figure 9-5 , each intersection between a word line and a bit line corresponds to one bit of "memory." If a diode is present at the intersection, a 1 is stored; otherwise, a Ois stored. If you were to build this circuit in the lab, you would "program" the memory by inserting and removing diodes at each intersection. Primitive though it may seem, owners of the DEC PDP-11 minicomputer (circa 1970) made use of similar technology in the M792 32x 16 "bootstrap ROM module." The module was shipped with 512 diodes soldered in place, and owners programmed it by clipping out the diode at each location where a O was to be stored. The diode pattern shown in Figure 9-5 corresponds to the 2-to-4-decoder truth table of Table 9-1. This doesn 't seem very efficient-we used a 3-to-8 decoder and a bunch of diodes to build the ROM version of a 2-to-4 decoder. We could have used a subset of the 3-to-8 decoder directly! However, we'll show a more efficient ROM structure and some more useful design examples later. ICTP FPGA-VHDL

12 Decodificación en Dos Dimensiones
g Suppose you wanted to build a 128 x 1 ROM using the kind of structure described in the preceding subsection. Have you ever thought about what it would take to build a 7-to-128 decoder? Try input NANO gates to begin with, and add 14 buffers and inverters with a fanout of 64 each! ROMs with million of bits or more are available commercially; trust me, they do not contain 20-to-1 ,048,576 decoders or worse. Instead, a different structure, called two dimensional decoding, is used to reduce the decoder size to something on the order of the square root of the number of addresses. The basic idea in two-dimensional decoding is to an-ange the ROM cells in an array that is as close as possible to square. For example, Figure 9-7 shows a possible internal structure for a 128 x 1 ROM. The three high-order address bits, A6- A4, are used to select a row. Each row stores 16 bits starting at address (A6, A5, A4, 0, 0, 0, 0). When an address is applied to the ROM, all 16 bits in the selected row are "read out" in parallel on the bit lines. A 16-input multiplexer selects the desired data bit based on the low-order address bits . By the way, the diode pattern in Figure 9-7 was not chosen at random. It performs a very useful 7-input combinational logic function that would require 35 4-input AND gates to build as a minimal two-level AND-OR circuit (see Exercise 9.7). The ROM version of this function could actually save a fair amount of engineering effort and space compared to a gate-level design. Two-dimensional decoding allows a 128 x 1 ROM to be built with a 3-to-8 decoder and a 16-input m·ultiplexer (whose complexity is comparable to that of a 4-to-16 decoder). A lMx 1 ROM could be built with a 10-to-1024 decoder and a 1024-input multiplexer-not easy, but a lot simpler than the one-dimensional alternative. Besides reducing decoding complexity, two-dimensional decoding has one other benefit-it leads to a chip whose physical dimensions are close to square, important for chip fabrication and packaging. A chip with a lM x 1 physical array would be very long and skinny and could not be built economically. ICTP FPGA-VHDL

13 ROM con Transistores MOS ROMs actually use a transistor instead of a diode at each location where a bit is to be stored; Figure 9-8 shows the basic idea. The row decoder has active-high outputs. When a row line is asserted, the NMOS transistors in that row are turned on, which pulls the corresponding bit lines low. A similar idea can be used in ROMs built with bipolar transistors. ICTP FPGA-VHDL

14 ROM de Múltiple Salidas (32K x 8)
In ROMs with multiple data outputs, the storage arrays corresponding to each data output may be made narrower in order to achieve an overall chip layout that is closer to square. For example, Figure 9-9 shows the possible layout of a 32K x 8 ROM chip ICTP FPGA-VHDL

15 Tecnología usada en las ROMs
ROM Programada por Máscara La memoria ROM es fabricada por el fabricante de CI usando un patrón de conexiones y no conexiones, llamado mascara, generado por el diseñador (cliente) El fabricante de CI usa esta información para crear una ROM dedicada, siguiendo el patrón provisto por el diseñador Most of the early integrated-circuit ROMs were mask-programmable ROMs (or, simply, mask ROMs). A mask ROM is programmed by the pattern of connections and no-connections in one of the masks used in the IC manufacturing process. To program or write information into the ROM, the customer gives the manufacturer a listing of the desired ROM contents, using a floppy disk or other transfer medium. The manufacturer uses this information to create one or more customized masks to manufacture ROMs with the required pattern. ROM manufacturers impose a mask charge of several thousand dollars for the "customized" aspects of mask-ROM production. Because of mask charges and the four-week delay typically required to obtain programmed chips, mask ROMs are normally used today only in very high-volume applications. For low-volume applications there are more cost-effective choices, discussed next Debido a que la ROM fabricada, es una memoria de uso especifico, basada en el patrón de conexiones provisto por el diseñador, el costo de la mascara es muy alto. Por lo que únicamente se justifica usar esta tecnología para muy altos volúmenes de producción ICTP FPGA-VHDL

16 Tecnología usada en las ROMs (2)
ROM Programable - PROM En esta tecnología se usa un programador de ROM para ‘programar’ la ROM La memoria tipo PROM se fabrica con todos sus transistores o diodos conectados. Así, todos los bits de la memoria tienen un valor lógico definido, típicamente ‘1’ El programador PROM es utilizado para cambiar el valor de fabrica por el valor opuesto. En tecnología bipolar (TTL) este proceso se realizaba al vaporizar un pequeño fusible de unión existente en cada cruce de la línea de palabra y la columna de bit A programmable read-only memory (PROM) is similar to a mask ROM, except that the customer may store data values (i.e., "program the PROM") in just a few minutes using a PROM programmer. A PROM chip is manufactured with all of its diodes or transistors "connected." This corresponds to having all bits at a particular value, typically 1. The PROM programmer can be used to set desired bits to the opposite value. In bipolar PROMs, this is done by vaporizing tiny fusible links inside the PROM corresponding to each bit. A link is vaporized by selecting it using the PROM's address and data lines, and then applying a high-voltage pulse ( V) to the device through a special input pin. Early bipolar PROMs had reliability problems. Sometimes the stored bits changed because of incompletely vaporized links that would "grow back," and sometimes intermittent failures occurred because of floating shrapnel inside the IC package. However, these problems were worked out, and reliable fusible-link technology was later used not only in bipolar PROMs, but also in the bipolarPLD circuits that we describe in Section BiPLD in DDPPonline. Con este tipo de tecnología, una vez programada la ROM no se puede modificar, ya que el fusible quedo abierto o cerrado. Este tipo de memorias se les llama OTPROM (One Time Programmable ROM) ICTP FPGA-VHDL

17 Tecnología usada en las ROMs (3)
ROM Programable Borrable - EPROM Con esta tecnología se puede programar una ROM, similar a la PROM, pero también se puede borrar (en realidad volver al estado inicial al exponer el CI a la luz ultravioleta) EPROMs usan un transistor especial llamado ‘puerta-flotante MOS’ (floating-gate MOS). Este tipo de transistores son construidos con materiales que son sensibles a la luz ultravioleta. Este tipo de memorias tienen un encapsulado especial, tienen una ‘ventana’ por al cual se hace pasar luz ultravioleta cuando se desea borrar la configuración de la memoria (típicamente durante unos 20 minutos). Durante el uso normal, esa ventana se debe tapar a fin de evitar borrado no deseado Introduced later, an erasable programmable read-only memory (EPROM) can be programmed like a PROM, but can also be "erased" to the all- ls state by exposing it to ultraviolet light. No, the light does not cause fuses to grow back! Rather, EPROMs use a different technology, called "floating-gate MOS." As shown in Figure 9-10, an EPROM has afloating-gate MOS transistor at every bit location. Each transistor has two gates. The "floating" gate is not connected and is surrounded by extremely high-impedance insulating material. To program an EPROM, the programmer applies a high voltage to the nonfloating gate at each bit location where a Ois to be stored. This causes a temporary breakdown in the insulating material and allows a negative charge to accumulate on the floating gate. When the high voltage is removed, the negative charge remains. During subsequent read operations, the negative charge prevents the MOS transistor from turning on when it is selected. EPROM manufacturers "guarantee" that a properly programmed bit will retain 70% of its charge for at least 10 years, even if the part is stored at 125°C, so EPROMs definitely fall into the category of "nonvolatile memory." However, they can also be erased. The insulating material surrounding the floating gate becomes slightly conductive if it is exposed to ultraviolet light with a certain wavelength. Thus, EPROMs can be erased by exposing the chips to ultraviolet light, typically for 5-20 minutes, when the chip is housed in a package with a transparent quartz lid. At one time, the most common application of EPROMs was to store programs in microprocessor systems. EPROMs were typically used during program development, where the program or other information in the EPROM must be repeatedly changed during debugging. However, ROMs and PROMs usually cost less than EPROMs of similar capacity. Therefore, once a program is finalized, a ROM or PROM may be used in production to save cost. Most of today's PROMs are actually EPROMS housed in inexpensive plastic packages without quartz lids for erasing; these are called one-time programmable (OTP) ROMs. Obviamente, este tipo de tecnología es el mas caro de visto para memorias ROM. Por ende, este tipo de memoria se usa durante la etpa de depuración del diseño, y para la versin final se usa una ROM (OTPROM) ICTP FPGA-VHDL

18 Tecnología usada en las ROMs (4)
ROM Programable Eléctricamente Borrable - EEPROM Esta tecnología es similar a la EPROM, pero en este caso la memoria se puede borrar eléctricamente En los tamaños de memoria EEPROM mayores a 1Mbit, el borrado se hace por bloques (no por bits o palabras). Tipicamente bloques de KBytes por vez. Es por esto que a este tipo de memorias se las conoce como ‘Memorias Flash’, poruqe un bloque entero de memoria puede ser borrado rápidamente (‘in a flash’) La principal desventaja de este tipo de memorias es que la escritura de datos es mucho mas lenta que la lectura. Y tiene un limite de unos ciclos de Rd/Wr por locación de memoria Algunas EEPROM son fabricadas con una interface serie (de tres cables) para aplicaciones espaciales tales como mantener la configuración de una FPGA, palabras calves de algunas aplicaciones, códigos encriptados, etc. An electrically erasable programmable read-only memo,y (EEPROM) is like an EPROM, except that individual stored bits may be erased electrically. The floating gates in an EEPROM are sunounded by a much thinner insulating layer and can be erased by applying a voltage of the opposite polarity as the charging voltage to the nonfloating gate. Large EEPROMs (1 Mbit or larger) allow erasing only in fixed-size blocks, typically Kbits ( Kbytes) at a time. These memories are usually called flash EPROMs or flash memories, because an entire block can be erased "in a flash." As noted in Table 9-5 on page 810, writing an EEPROM location takes much longer than reading it, so an EEPROM is no substitute for the read/write memories discussed later in this chapter. Also, because the insulating layer is so thin, it can be worn out by repeated programming operations. As a result, EEPROMs can be reprogrammed only a limited number of times, as few as 10,000 times per location. Therefore, EEPROMs are typically used for storing data that must be preserved when the equipment is not powered, but that doesn't change very often, such as the default configuration data for a computer. Much smaller ROMs are also produced with 3-bit serial interfaces for specialized applications, such as downloading the programming information into FPGAs. Multiple flash memories are often packaged into a single credit-card-size module for applications requiring large amounts of nonvolatile storage. The most common application of these modules is in digital cameras, where storing a single uncompressed high-resolution image may require 10 Mbytes or more of storage. In 2005, the largest flash card was sold by industry leader SanDisk Corporation and contained 4 Gbytes (32,768 Mbits) of memory Múltiples memorias flash son empaquetadas en un formato pequeño para aplicaciones que requieren una gran cantidad de memoria no-volátil. Ejemplo muy típico son las memorias tipo SD Card, y los pen drives ICTP FPGA-VHDL

19 ROM – Entradas de Control
Las memorias ROM normalmente se usan en sistemas donde existe un bus al cual están conectados otros CI, por lo tanto la mayoría de las ROMs tienen disponibles entrada de control para salidas tres-estados Esta entrada se comúnmente se denomina habilitación de salida, output-enable, y se simboliza con las letras OE OE debe ser asertiva para habilitar las salidas The outputs of a ROM must often be connected to a three-state bus, where different devices may drive the bus at different times. Therefore, most commercial ROM chips have three-state data outputs and an output-enable (OE) input that must be asserted to enable the outputs. Many ROM applications, especially program storage, have multiple ROMs connected to a bus, where only one ROM drives the bus at a time. Most ROMs have a chip-select (CS) in.put to simplify the design of such systems. In addition chip-select (CS) input to OE, a ROM's CS input must be asserted to enable the three-state outputs Otra entrada de control que se usa en las ROM es una entrada que habilita la ROM en si. Esta señal de control se denomina selector de integrado, chip-select, y se simboliza con las letras CS Tanto CS como OE deben ser asertivas para habilitar las salidas ICTP FPGA-VHDL

20 ROM – Entradas de Control – Ejemplo de Uso
Figure 9-12 shows how the OE and CS inputs could be used when connecting four 32K x 8 EEPROMs to an 8-bit microprocessor system that requires 128 Kbytes of EEPROM. The microprocessor has an 8-bit data bus and a 20-bit address bus, for a maximum address space of 1 Mbyte (220 bytes). The EEPROM is supposed to be located in the highest 128K of the address space. To obtain this behavior, a NAND gate is used to produce the HIMEM_L signal, which is asserted when the address bus contains an address in the highest 128K (A19-A17 = 111). A 74x139 2-to-4 decoder then selects one of the four 32K x 8 EEPROMs. The selected EEPROM drives the data bus only when the microprocessor requests a read operation by asserting READ, which is connected to all of the OE inputs. In this application, the microprocessor's WRITE output is hooked up to the EEPROMs' WE (write-enable) inputs. This signal is used during EEPROM programming operations, for example, to load new code into the device. As we've described it so far, a CS input is no more than a second output enable input that is ANDed with OE to enable the three-state outputs. However, in many ROMs, CS also serves as a power-down input. When CS is negated, power is removed from the ROM's internal decoders, drivers, and multiplexers. ICTP FPGA-VHDL

21 ROM – Timing Diagram tAA(tiempo de acceso desde dirección): retardo de propagación desde que la dirección de entrada es estable hasta que haya una salida valida tACS(tiempo de acceso desde chip select): retardo de propagación desde que la entrada CS es estable hasta que haya una salida valida tAA Access time from address. The access time from address of a ROM is the propagation delay from stable address inputs to valid data outputs. When designers talk about "a 100-ns ROM," they are usually referring to this parameter. tACS Access time from chip select. The access time from chip select of a ROM is the propagation delay from the time CS is asserted until the data outputs are valid. In some chips, this is longer than the access time from address, because the chip takes a little while to "power up." In others, this time is shorter because CS controls only output enabling. toE Output-enable time. This parameter is usually much shorter than access time. The output-enable time of a ROM is the propagation delay from OE and CS both asserted until the three-state output drivers have left the Hi-Z state. Depending on whether the address inputs have been stable long enough, the output data may or may not be valid at that point. toz Output-disable time. The output-disable time of a ROM is the propagation delay from the time OE or CS is negated until the three-state output drivers have entered the Hi-Z state. toH Output-hold time. The output-hold time of a ROM is the length of time that the outputs remain valid after a change in the address inputs, or after OE_L or CS_L is negated. tOE(tiempo de habilitación de salida): retardo de propagación desde que ambas entradas CS y OE han sido asertivas hasta que los buffers de salida dejaron el tercer estado tOZ(tiempo de des-habilitación de salida): retardo de propagación desde que alguna de las entradas CS y OE han sido negadas hasta que los buffers de salida entraron en el tercer estado tOH(tiempo de mantenimiento de salidas): es el tiempo que las salidas permanecen validas despues de un cambio en las direcciones de entrads o luego de que OE_L o CS_L has sido negadas ICTP FPGA-VHDL

22 ROM – Ventajas/Desventajas de Uso
Pros Para funciones lógicas de complejidad moderada, un circuito basado en ROM es normalmente mas rápido que uno usando compuertas lógicas, o FPGAs La función lógica almacenada en la ROM es fácilmente modificable, sin tener que cambiar el hardware (en la mayoia de los casos, no siempre… ) El precio de las ROMs continua bajando, al mismo tiempo que el tamaño de las mismas se va incrementando Máquinas de estados basadas en ROM (microprogramación) son muy eficientes, alto rendimiento y bajo consumo Cons Para funciones lógicas pequeñas, un circuito basado en ROM puede ser mas caro, consumir mas potencia o ser mas lento que uno construido con lógica discreta o FPGA In addition to ease and speed of design, a ROM-based circuit has other important advantages: • For a moderately complex function, a ROM-based circuit is usually faster than a circuit using multiple SSI/MSI devices and PLDs, and often faster than an FPGA or custom LSI chip in a comparable technology. • The program that generates the ROM contents can easily be structured to handle unusual or undefined cases that would require additional hardware in any other design. For example, the adder program in Table 9-7 easily handles out-of-range sums. (Also see Exercise 9.22.) • A ROM's function is easily modified just by changing the stored pattern, usually without changing any external connections. For example, the PCM attenuator and adder ROMs in this subsection can be changed to use 8-bit A-law PCM, the standard digital voice coding in Europe. • The prices of ROMs and other structured logic devices are always falling, making them more economical, and their densities are always increasing, expanding the scope of problems that can be solved with a single chip. There are a few disadvantages of ROM-based circuits, too: • For simple to moderately complex functions, a ROM-based circuit may cost more, consume more power, or run slower than a circuit using a few SSI/MSI devices and PLDs or a small FPGA. ICTP FPGA-VHDL

23 Memorias de Lectura/Escritura
Una memoria de lectura y escritura permite escribir y leer los datos en cualquier momento Este tipo de memoria se las conoce como memoria de acceso aleatorio (Random Access Memory, RAM), lo que significa que toma el mismo tiempo la lectura o escritura de un bit de la memoria, independientemente de la locación del bit en la memoria The name read/write memory (RWM) is given to memory arrays in whjch we can store and retrieve information at any time. Most of the RWMs used in digital systems nowadays are random-access memories (RAMs) , which means that the time it talces to read or write a bit is independent of the bit's location in the RAM. From this point of view, ROMs are also random-access memories, but the name "RAM" is generally used only for read/write random-access memories. Basado en el funcionamiento de una ROM, también puede decirse que una ROM es una RAM, pero el nombre RAM se usa generalmente para las memorias de escritura/lectura ICTP FPGA-VHDL

24 Memorias de Lectura/Escritura
RAM SRAM SSRAMS DRAM SDRAM SDDR-RAM In a static RAM (SRAM) (''S-ram"), once a word is written at a location, it remains stored as long as power is applied to the chip, unless the same location is written again. In a dynamic RAM (DRAM) ("D-ram"), the data stored at each location must be refreshed periodically by reading it and then writing it back again, or else it disappears. We' ll discuss both types in thfa section. Most RAMs lose their memory when power is removed; they are a form of volatile memory. Some RAMs retain their memory even when power is removed; they are called nonvolatile memory. Examples of nonvolatile RAMs are old-style magnetic core memories and modern CMOS static memories in an extra-large package that includes a lithium battery with a 10-year lifetime ICTP FPGA-VHDL

25 RAM Estática - SRAM Read: una dirección es colocada en la entrada de direcciones (A0…An-1), mientras las entradas CS y OE son asertivas. El contenido de la dirección de memoria estará disponible en las salidas DOUT0..DOUTb-1 Write: una dirección es colocada en la entrada de direcciones (A0…An-1), y un dato es colocado en las entradas de datos DIN0…DINb-1, luego CS and OE son asertadas. El dato es así almacenado en la respectiva locación de memoria. Like a ROM, a RAM has address and control inputs and data outputs, but it also has data inputs. The inputs and outputs of a simple 2n x b-bit static RAM are shown in Figure The control inputs are comparable to those of a ROM, with the addition of a write-enable (WE) input. When WE is asserted, the data inputs are written into the selected memory location. The memory locations in a static RAM behave like D latches, rather than edge-triggered D flip-flops. This means that whenever the WE input is asserted, the latches for the selected memory location are "open" (or "transparent"), and input data flows into and through the latch. The actual value stored is whatever is present when the latch closes. ICTP FPGA-VHDL

26 Estructura de una SRAM During read operations, the output data is a combinational function of the address inputs, as in a ROM. o harm is done by changing the address lines while the output data bus is enabled. The access time for read operations is specified from the time that the last address input becomes stable. • During write operations, the input data is stored in latches. This means that the data must meet certain setup and hold times with respect to the trailing edge of the latch enable signal. That is, the input data at a latch's D input need not be stable at the moment WR_L is asserted internally; it must only be stable a certain time before WR_L is negated. • During write operation , the address inputs must be stable for a certain setup time before WR_L is as erted internally and for a hold time after WR_L is negated. Otherwise, data may be "sprayed" all over the array because of the glitches that may appear on the SEL_L lines when the address inputs of the decoder are changing. • Internally, WR_L is asserted only when both CS_L and WE_L are asserted. Therefore, a write cycle begins when both CS_L and WE_L are asserted write cycle and ends when either is negated. Setup and hold times for address and data are specified with respect to these events. ICTP FPGA-VHDL

27 Parámetros de Tiempo de Escritura de RAM
tAS(tiempo de establecimiento antes de escribir): todas las entradas de direcciones deben ser estable por lo menos en este tiempo antes que CS y OE sean asertivas Timing parameters for write operations are shown in Figure 9-23 and are described below: tAS Address setup time before write. All of the address inputs must be stable at this time before both CS and WE are asserted. Otherwise, the data stored at unpredictable locations may be corrupted. tAH Address hold time after write. Analogous to tAs, all address inputs must be held stable until this time after CS or WE is negated. tcsw Chip-select setup before end of write. CS must be asserted at least this long before the end of the write cycle in order to select a cell. twp Write-pulse width. WE must be asserted at least this long to reliably latch data into the selected cell. tDS Data setup time before end of write. All of the data inputs must be stable at this time before the write cycle ends. Otherwise, the data may not be latched. tDH Data hold time after end of write. Analogous to t0 s, all data inputs must be held stable until this time after the write cycle ends. tAH(tiempo de sostenimiento después de escribir): todas las entradas de direcciones deben ser mantenidas estables por lo menos por este tiempo antes que CS y OE sean negadas tCSW(tiempo de establecimiento antes del fin de escritura): CS debe ser asertiva por lo menos por este tiempo antes del fin del ciclo de escritura tWP(ancho del pulso de escritura): WE debe ser asertiva por lo menos por este tiempo ICTP FPGA-VHDL

28 Parámetros de Tiempo de Escritura de RAM (cont.)
tDS(tiempo de establecimiento antes del fin de escritura): Todos los DATOS de entrada deben ser estables a este tiempo antes que termine el ciclo de escritura Timing parameters for write operations are shown in Figure 9-23 and are described below: tAS Address setup time before write. All of the address inputs must be stable at this time before both CS and WE are asserted. Otherwise, the data stored at unpredictable locations may be corrupted. tAH Address hold time after write. Analogous to tAs, all address inputs must be held stable until this time after CS or WE is negated. tcsw Chip-select setup before end of write. CS must be asserted at least this long before the end of the write cycle in order to select a cell. twp Write-pulse width. WE must be asserted at least this long to reliably latch data into the selected cell. tDS Data setup time before end of write. All of the data inputs must be stable at this time before the write cycle ends. Otherwise, the data may not be latched. tDH Data hold time after end of write. Analogous to t0 s, all data inputs must be held stable until this time after the write cycle ends. tDH(tiempo de sostenimiento antes del fin de escritura): Todos los DATOS de entrada deben ser estables por lo menos por este tiempo después que termine el ciclo de escritura ICTP FPGA-VHDL

29 RAM Comerciales 8K x 8 32K x 8 512K x 8 128K x 8 ICTP FPGA-VHDL

30 RAM Dinámica Para poder construir memorias mas grandes y sobre todo mas baratas, se recurrió a almacenar la información de cada bit de la memoria en un pequeñísimo capacitor controlado por un transistor MOS The basic memory cell in an SRAM, a D latch, requires four gates in a discrete design, and four to six transistors in a custom-designed SRAM LSI chip. In order to build RAMs with higher density (more bits per chip), chip designers invented memory cells that use as little as one transistor per bit. 9.4.1 Dynamic-RAM Structure It is not possible to build a bistable element with just one transistor. Instead, the memory cells in a dynamic RAM (DRAM) store information on a tiny capacitor accessed through a MOS transistor. Figure 9-31 shows the storage cell for one bit of a DRAM, which is accessed by setting the word line to a HIGH voltage. To store a 1, the bit is accessed and a HIGH voltage is placed on the bit line, which charges the capacitor through the "on" transistor. To store a 0, a LOW voltage placed on the bit line discharges the capacitor. To read a DRAM cell, the bit line is first precharged to a voltage halfway between HIGH and LOW, and then the word line is set HIGH. Depending on whether the capacitor voltage is HIGH or LOW, the precharged bit line is pulled slightly higher or slightly lower. A sense amplifier detects this small change and recovers a 1 or O accordingly. ote that reading a cell destroys the original voltage stored on the capacitor, so that the recovered data must be written back into the cell after reading. The capacitor in a DRAM cell has a very small capacitance, but the MOS transistor that accesses it has a very high impedance. Therefore, it takes a relatively long time (100 milliseconds or more) for a HIGH voltage to discharge to the point that it looks more like a LOW voltage. In the meantime, the capacitor stores one bit of information. Naturally, using a computer would be no fun if you had to reboot every 100 milliseconds because its memory contents disappeared (the typical behavior of some operating systems notwithstanding). Therefore, DRAM-based memory systems use refresh cycles to update every memory cell periodically, typically once every 64 milliseconds. This involves sequentially reading the somewhat degraded contents of each cell into a D latch and writing back a nice solid LOW or HIGH value from the latch. Figure 9-32 illustrates the electrical state of a cell after a write and a sequence of refresh operations ICTP FPGA-VHDL

31 Ciclo de Refresco El capacitor de la DRAM tarda unos 100 milisegundos para descargarse a través del transistor MOS, mientras tanto el capacitor almacena un ‘1’ Las memorias DRAM tienen un ‘ciclo de refresco’, durante el cual, cada 64 milisegundos se ‘refresca’ la carga del capacitor The capacitor in a DRAM cell has a very small capacitance, but the MOS transistor that accesses it has a very high impedance. Therefore, it takes a relatively long time (100 milliseconds or more) for a HIGH voltage to discharge to the point that it looks more like a LOW voltage. In the meantime, the capacitor stores one bit of information. Naturally, using a computer would be no fun if you had to reboot every 100 milliseconds because its memory contents disappeared (the typical behavior of some operating systems notwithstanding). Therefore, DRAM-based memory systems use refresh cycles to update every memory cell periodically, typically once every 64 milliseconds. This involves sequentially reading the somewhat degraded contents of each cell into a D latch and writing back a nice solid LOW or HIGH value from the latch. Figure 9-32 illustrates the electrical state of a cell after a write and a sequence of refresh operations. The first DRAMs, introduced in the early 1970s, contained only 1024 bits, but modern DRAMs are available containing 512 megabits or more. If you had to refresh every cell, one at a time, in 64 milliseconds, you'd have a problemthat works out to far less than 1 ns per cell, and includes no time for useful read and write operations. Fortunately, as we'll show, DRAMs are organized using two-dimensional aJ.Tays, and a single operation refreshes an entire row of the array. EaJ.·ly DRAM arrays had 256 rows, requiring 256 refresh operations every four milliseconds, or one about every 15.6 µsec. ewer arrays have 4096 rows but need to be refreshed only once every 64 ms, which still works out to one row per 15.6 µsec. A refresh operation typically takes less than 100 ns, so the DRAM is available for useful read and write operations over 99% of the time La operación de refresco toma menos de 100 ns, por lo que las memorias DRAM están disponibles para operaciones de escritura o lectura el 99% del tiempo ICTP FPGA-VHDL

32 RAM Dinámica Sincrónica – Estructura Interna
Figure 9-33 is a block diagram of the internal structure of our example 4M x 4 DRAM. This device is called a synchronous DRAM (SDRAM) because its control and data operations are all referenced to a common clock signal, CLK. Older DRAMs had asynchronous control signals; for more information, see the third edition of this book. The logical array in Figure 9-33 has 4M x 4 bits, but the physical array is square, containing 4096 x 4096 bits. Many commercial DRAM chips have non square individual a1Tays, but multiple nonsquare arrays (banks) are arranged to yield an overall chip that is close to square. In the earliest SDRAMs, the clock signal CLK runs at 100 MHz; newer SDRAMs run at 200 MHz or more. Various commands, explained shortly, can be applied to the device on the 3-bit CMD bus at each rising edge of CLK. Although the example SDRAM has 4M (222) locations, the chip has only 12 multiplexed address inputs A[11 :OJ. A complete 22-bit address is presented to the chip in two steps at two clock ticks, as determined by operation codes on the CMD bus. Multiplexing the address inputs saves pins, impo11ant for compact design of memory systems, and also fits quite naturally with the two-step SDRAM access methods that we'll describe shortly. One advantage of having multiple banks in larger SDRAMs is to ease the electrical and physical design problems that would occur with a single, very large memory aiTay. But even more important is the parallelism that can occur when there are multiple banks. As we' ll see in the next subsection, SDRAM operation is much more complicated than SRAM operation. Taking advantage of the multiple banks in larger, high-speed SDRAMs, a modern SDRAM memory controller can perform several operations in parallel-for example, completing a write operation in one bank while initiating a read operation in another. This increases the effective throughput of the memory. ICTP FPGA-VHDL

33 Memorias Tipo Dual Data Rate (DDR)
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34 Double-Data-Rate (DDR) SDRAM
Este tipo de memorias transfiere el datos en ambos flancos del reloj, flanco positivo y flanco negativo Latencia Double-data-rate (DDR) SDRAMs do just that-they double the data-transfer rate of an SDRAM by transferring data on both edges of the clock, rising and falling. Note that address and command operations still require one clock cycle, the same as in a conventional SDRAM. So, the actual data-transfer rate is increased only for burst operations. DDR operation is "simple" from a functional point of view. For example, just imagine eight words conung out in the same interval that four are shown in the SDRAM burst cycles in Figures 9-36 and 9-37, with even-numbered words referenced to the rising edge of the clock, and odd-numbered to the falling edge. But DDR operation is very tricky from a timing and analog implementation point of view. Remember, the whole point of DDR is to go fast. To maintain precis e timing, DDR SDRAMs use differential clock inputs-complementary versions of the clock signal with very little timing skew between them. An onchip analog delay-locked loop (DLL) locks onto this clock signal and generates internal and external signals, including output data and input and output latch enables, with precise delays relative to this clock. Board-level designers must be very careful to balance the delays, minimize the skew, and optimize the quality of all signals going to and from the DOR SDRAM. Even after all this work, DDR operation provides faster data transfers only during burst-mode operations, so the benefit is application dependent. Burst Length La mayor ventaja del DDR es realmente cuando se transmiten datos en paquetes (burst), dado que tanto el direccionamiento de la memoria como el comando de operaciones trabajan igual que en la SDRAM ICTP FPGA-VHDL

35 Senal de Reloj de Alta Frecuencia
La integridad de la señal de los relojes de alta frecuencia son afectados por factores eléctricos, electromagnéticos, mecánicos, etc. Afectan el ciclo de trabajo del reloj (50% ‘1’, 50% ‘0’) Para memorias tipo SDR (single data rate) no es problema. Para DDR gran problema ICTP FPGA-VHDL

36 Señal Real de Reloj ICTP FPGA-VHDL

37 Señal de Reloj para DDR Para memorias tipo DDR normalmente se usa una señal de reloj de tipo diferencial. ICTP FPGA-VHDL

38 Señal de Captura (DQS) La velocidad de transferencia de los datos en una memoria DDR necesita de una señal de captura de datos para hacer mas confiable el dato ha ser escrito o leído DQS (D-Q-Strobe) es la señal de captura usada en DDR Señal bidireccional controlada por: Memoria: cuando el dato es leído de la memoria Controlador DDR: cuando el datos es escrito en la memoria ICTP FPGA-VHDL