Tecnología de las Familias Lógicas

Presentación del tema: "Tecnología de las Familias Lógicas"— Transcripción de la presentación:

1 Tecnología de las Familias Lógicas

2 Reseña Histórica En 1940, la primer computadora electrónica digital (ENIAC) tenia cerca de válvulas, para un número similar de compuertas lógicas A fines de los 50, la invención del diodo semiconductor y los transistores bipolares, permitieron el desarrollo de computadoras mas chicas, rápidas y mayor capacidad de computo oday’s standards of microprocessor chips with tens of millions of transistors. However, the Eniac could hurt you a lot more than a chip could if it fell on you—it was 100 feet long, 10 feet high, 3 feet deep, and consumed 140,000 watts of power! En los 60, la invención del Circuito Integrado (IC, Integrated Circuit), permitió incluir en una misma pastilla (IC) múltiples diodos, transistores, y otros componentes ICTP FPGA-VHDL

3 Familia Lógica Bipolar Transistor Transistor Logic (TTL)
Es una colección de diferentes circuitos integrados con sus entradas y salidas, construidos con la misma tecnología pero que tienen distinta funcionalidad lógica Circuitos integrados de una misma tecnología se pueden conectar entre sí Circuitos integrados de distintas tecnología puede que no se puedan conectar entre sí c labs; therefore, we introduce TTL families in Section 3.10. Ten years before the bipolar junction transistor was invented, the principles of operation were patented for another type of transistor, called the metal-oxide semiconductor field effect transistor (MOSFET), or simply MOS transistor. However, MOS transistors were difficult to fabricate in the early days, and it wasn’t until the 1960s that a wave of developments made MOS-based logic and memory circuits practical. Even then, MOS circuits lagged bipolar circuits considerably in speed, and were attractive only in selected applications because of their lower power consumption and higher levels of integration. Beginning in the mid-1980s, advances in the design of MOS circuits, in particular complementary MOS (CMOS) circuits, vastly increased their performance and popularity. By far the majority of new large-scale integrated circuits, such as microprocessors and memories, use CMOS. Likewise, small- to medium-scale applications, for which TTL was once the logic family of choice, are now likely to use CMOS devices with equivalent functionality but higher speed and lower power consumption. CMOS circuits now account for the vast majority of the worldwide IC market. CMOS logic is both the most capable and the easiest to understand commercial digital logic technology. Beginning in the next section, we describe the basic structure of CMOS logic circuits and introduce the most commonly used commercial CMOS logic families As a consequence of the industry’s transition from TTL to CMOS over a long period of time, many CMOS families were designed to be somewhat compatible with TTL. In Section 3.12, we show how TTL and CMOS families can be mixed within a single system. Familia Lógica Complementary Metal-Oxide Semiconductor Filed Effect Transistor (CMOS) Familia Lógica Bipolar Transistor Transistor Logic (TTL) ICTP FPGA-VHDL

4 Familia Lógica CMOS Transistor MOS NMOS PMOS
A MOS transistor can be modeled as a 3-terminal device that acts like a voltagecontrolled resistance. As suggested by Figure 3-7, an input voltage applied to one terminal controls the resistance between the remaining two terminals. In digital logic applications, a MOS transistor is operated so its resistance is always either very high (and the transistor is “off”) or very low (and the transistor is “on”) There are two types of MOS transistors, n-channel and p-channel; the names refer to the type of semiconductor material used for the resistance-controlled terminals. The circuit symbol for an n-channel MOS (NMOS) transistor is shown in Figure 3-8. The terminals are called gate, source, and drain. (Note that the “gate” of a MOS transistor has nothing to do with a “logic gate.”) As you might guess from the orientation of the circuit symbol, the drain is normally at a higher voltage than the source El transistor MOS puede ser visto como una resistencia controlado por un voltaje (tensión) ICTP FPGA-VHDL

5 Familia Lógica CMOS - NMOS
La tensión Vgs (gate to source) es positiva o cero A MOS transistor can be modeled as a 3-terminal device that acts like a voltagecontrolled resistance. As suggested by Figure 3-7, an input voltage applied to one terminal controls the resistance between the remaining two terminals. In digital logic applications, a MOS transistor is operated so its resistance is always either very high (and the transistor is “off”) or very low (and the transistor is “on”) There are two types of MOS transistors, n-channel and p-channel; the names refer to the type of semiconductor material used for the resistance-controlled terminals. The circuit symbol for an n-channel MOS (NMOS) transistor is shown in Figure 3-8. The terminals are called gate, source, and drain. (Note that the “gate” of a MOS transistor has nothing to do with a “logic gate.”) As you might guess from the orientation of the circuit symbol, the drain is normally at a higher voltage than the source Si Vgs = 0 La resistencia Drain to Source (Rds) es muy alta, del orden de un megahom o más Si Vgs > 0 A medida que se incrementa Vgs, Rds decrece a valores muy bajos, 10 Ohms o menos ICTP FPGA-VHDL

6 Familia Lógica CMOS - PMOS
La tensión Vgs (gate to source) es negativa o cero A MOS transistor can be modeled as a 3-terminal device that acts like a voltagecontrolled resistance. As suggested by Figure 3-7, an input voltage applied to one terminal controls the resistance between the remaining two terminals. In digital logic applications, a MOS transistor is operated so its resistance is always either very high (and the transistor is “off”) or very low (and the transistor is “on”) There are two types of MOS transistors, n-channel and p-channel; the names refer to the type of semiconductor material used for the resistance-controlled terminals. The circuit symbol for an n-channel MOS (NMOS) transistor is shown in Figure 3-8. The terminals are called gate, source, and drain. (Note that the “gate” of a MOS transistor has nothing to do with a “logic gate.”) As you might guess from the orientation of the circuit symbol, the drain is normally at a higher voltage than the source Si Vgs = 0 La resistencia Drain to Source (Rds) es muy alta, del orden de un megahom o más Si Vgs < 0 A medida que se incrementa Vgs, Rds decrece a valores muy bajos, 10 Ohms o menos ICTP FPGA-VHDL

7 Familia Lógica CMOS – Muy Baja Corriente
Independientemente del voltaje aplicado a Vgs, no hay corriente que fluya desde el gate a source o desde gate a drain La resistencia entre el gate y los otros terminales (source o drain) es extremadamente alta Por ende la corriente que fluya a través de la resistencia es muy pequeña , típicamente del orden de los microamperes (µA, 10-6 A), y es llamada corriente de perdida (leakage current) ICTP FPGA-VHDL

8 Niveles Lógicos CMOS Abstract logic elements process binary digits, 0 and 1. However, real logic circuits process electrical signals such as voltage levels. In any logic circuit, there is a range of voltages (or other circuit conditions) that is interpreted as a logic 0, and another, nonoverlapping range that is interpreted as a logic 1. A typical CMOS logic circuit operates from a 5-volt power supply. Such a circuit may interpret any voltage in the range 0–1.5 V as a logic 0, and in the range 3.5–5.0 V as a logic 1. Thus, the definitions of LOW and HIGH for 5-volt CMOS logic are as shown in Figure 3-6. Voltages in the intermediate range are not expected to occur except during signal transitions, and yield undefined logic values (i.e., a circuit may interpret them as either 0 or 1). CMOS circuits using other power supply voltages, such as 3.3 or 2.7 volts, partition the voltage range similarly. ICTP FPGA-VHDL

9 Inversor CMOS Un transistor PMOS y uno NMOS son usados juntos para formar un Inversor CMOS NMOS and PMOS transistors are used together in a complementary way to form CMOS logic. The simplest CMOS circuit, a logic inverter, requires only one of each type of transistor, connected as shown in Figure 3-10(a). The power supply voltage, VDD, typically may be in the range 2–6 V, and is most often set at 5.0 V for compatibility with TTL circuits. Ideally, the functional behavior of the CMOS inverter circuit can be characterized by just two cases tabulated in Figure 3-10(b): 1. V IN is 0.0 V. In this case, the bottom, n-channel transistor Q1 is off, since its V gs is 0, but the top, p-channel transistor Q2 is on, since its Vgs is a large negative value (−5.0 V). Therefore, Q2 presents only a small resistance between the power supply terminal (VDD, +5.0 V) and the output terminal (VOUT), a 2. V IN is 5.0 V. Here, Q1 is on, since its Vgs is a large positive value (+5.0 V), but Q2 is off, since its Vgs is 0. Thus, Q1 presents a small resistance between the output terminal and ground, and the output voltage is 0 V. With the foregoing functional behavior, the circuit clearly behaves as a logical inverter, since a 0-volt input produces a 5-volt output, and vice versa nd the output voltage is 5.0 V. ICTP FPGA-VHDL

10 Compuerta NAND CMOS Both NAND and NOR gates can be constructed using CMOS. A k-input gate uses k p-channel and k n-channel transistors. Figure 3-13 shows a 2-input CMOS NAND gate. If either input is LOW, the output Z has a low-impedance connection to V DD through the corresponding “on” p-channel transistor, and the path to ground is blocked by the corresponding “off” n-channel transistor. If both inputs are HIGH, the path to VDD is blocked, and Z has a low-impedance connection to ground. Figure 3-14 shows the switch model for the NAND gate’s operation ICTP FPGA-VHDL

11 Compuerta NOR CMOS Figure 3-15 shows a CMOS NOR gate. If both inputs are LOW, the output Z has a low-impedance connection to VDD through the “on” p-channel transistors, and the path to ground is blocked by the “off” n-channel transistors. If either input is HIGH, the path to VDD is blocked, and Z has a low-impedance connection to ground. ICTP FPGA-VHDL

12 ?? ICTP FPGA-VHDL

13 Parámetros Eléctricos y de Tiempo
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14 Fan In – Fan Out El número de entradas que puede tener una compuerta de una familia lógica es llamada cargabilidad de entrada (fan in) El número de entradas que puede son conectadas a una determinada salida de una familia lógica es llamada cargabilidad de salida (fan out) The number of inputs that a gate can have in a particular logic family is called the logic family’s fan-in. CMOS gates with more than two inputs can be obtained by extending series-parallel designs on Figures 3-13 and 3-15 in the obvious manner. For example, Figure 3-16 shows a 3-input CMOS NAND gate. In principle, you could design a CMOS NAND or NOR gate with a very large number of inputs. In practice, however, the additive “on” resistance of series transistors limits the fan-in of CMOS gates, typically to 4 for NOR gates and 6 for NAND gates. Fanout. This refers to the number and type of inputs that are connected to a given output. If too many inputs are connected to an output, the DC noise margins of the circuit may be inadequate. Fanout may also affect the speed at which the output changes from one state to another. ICTP FPGA-VHDL

15 Definiciones Eléctricas de los CMOS
Niveles de Voltaje Lógicos: Los CI CMOS operando en condiciones normales garantizan producir niveles lógicos de salida dentro de los rangos definidos para esta tecnología ICTP FPGA-VHDL

16 Margen de Ruido (DC Noise Margin)
DC noise margin es una medida de cuanto ruido es necesario para corromper el valor de tensión de salida en el peor caso a un valor que no pueda ser reconocido correctamente por una entrada VILmax = 1.35V (0.3*(5V-10%Vcc) Margen de Ruido para ‘0’ lógico es de 1.25V VOLmax = 0.1V VIHmin = 3.15V (0.7*(5V-10%Vcc) Margen de Ruido para ‘1’ lógico es de 1.25V VOHmin = 4.4V (5V-10%Vcc-0.1V) ICTP FPGA-VHDL

17 Ruido (Noise) Hay diversas fuentes de ruido que pueden generar problemas en el funcionamiento de un sistema digital. Entre las principales fuentes de ruido se destacan: Campos magnéticos/eléctricos Perturbaciones en la fuente de voltaje Rayos cósmicos Conmutación de varias señales lógicas al mismo tiempo Rebote de señales debido a una adaptación de impedancias no correcta entre la salida del CI y la pista del circuito impreso ICTP FPGA-VHDL

18 Ruido (Noise) - 1 Señal real en un circuito real…. ICTP FPGA-VHDL

19 Ruido (Noise) - 2 Señal real en un circuito real…. ICTP FPGA-VHDL

20 Hoja de Datos – Parámetros más Importantes
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21 Corriente Máxima a Absorber por un CMOS
IOLmax : corriente máxima que la salida puede absorber en el estado lógico ‘0’, mientras mantiene la tensión de salida no mayor a VOLmax ICTP FPGA-VHDL

22 Corriente Máxima a Drenar por un CMOS
IOHmax : corriente máxima que la salida puede drenar en el estado lógico ‘1’, mientras mantiene la tensión de salida no menor a VOHmin ICTP FPGA-VHDL

23 Flujo de Corriente Positivo / Negativo
Por convención cuando la corriente medida a la salida de un CI fluye hacia dentro del dispositivo, se considera flujo positivo de corriente. Por ellos es que la corriente que es drenada por el CI, tiene un signo negativo en la hoja de datos del CI ICTP FPGA-VHDL

24 Entradas No Usadas ometimes not all of the inputs of a logic gate are used. In a real design problem, you may need an n-input gate but have only an n+1-input gate available. Tying together two inputs of the n+1-input gate gives it the functionality of an n-input gate. You can convince yourself of this fact intuitively now, or use switching algebra to prove it after you’ve studied Section 4.1. Figure 3-35(a) shows a NAND gate with its inputs tied together. You can also tie unused inputs to a constant logic value. An unused AND or NAND input should be tied to logic 1, as in (b), and an unused OR or NOR input should be tied to logic 0, as in (c). In high-speed circuit design, it’s usually better to use method (b) or (c) rather than (a), which increases the capacitive load on the driving signal and may slow things down. In (b) and (c), a resistor value in the range 1–10 kΩ is typically used, and a single pull-up or pull-down resistor can serve multiple unused inputs. It is also possible to tie unused inputs directly to the appropriate power-supply rail. En CI con tecnología CMOS las entradas no usadas nunca deberían dejarse sin conexión ICTP FPGA-VHDL

25 Descarga Electrostática (ESD)
Electrostatic Discharge (ESD) es un fenómeno eléctrico que hace que circule una corriente eléctrica repentina y momentánea entre dos objetos de distinto potencial eléctrico. Esta corriente eléctrica es indeseada y pueden causar daño irreparable al CI y/o al equipo electrónico ICTP FPGA-VHDL

26 Fuentes de ESD y Humedad Relativa
RH: Humedad relativa ICTP FPGA-VHDL

27 Protección y Prevención de ESD
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28 Bolsas Anti-estáticas
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29 Salidas Open-Drain en CMOS
Algunos CI CMOS omiten el transistor PMOS de la salida. Esto es usado en algunas aplicaciones tales como: Level Shifter ICTP FPGA-VHDL

30 CI con Salidas Tres-Estados (Three-States)
Algunos CI CMOS tiene una señal de entrada de control que puede ser usada para deshabilitar ambos transistores el PMOS y el NMOS. En este caso la salida tiene un valor que no es ni ‘1’ ni ‘0’, por lo que se dice que está en un tercer estado eléctrico llamado estado de alta impedancia (representado por ‘Z’) En el estado de alta impedancia la salida del CI se comporta como si no estuviera conectada a ninguna otra entrada u otro circuito CI con salidas tres-estados tienen una entrada extra comúnmente llamada ‘habilitación de salida (output enable, OE)”. Cuando esta señal es activa (ya sea por un ‘1’ o un ‘0’, dependiendo del caso) la(s) salida(s) del CI pasan a ‘Z’ ICTP FPGA-VHDL

31 CI con Salidas Tres-Estados
Circuito Interno de un Buffer three-state Buffer three-state The logic symbols for four physically different three-state buffers are shown in Figure The basic symbol is that of a noninverting buffer (a, b) or an inverter (c, d). The extra signal at the top of the symbol is a three-state enable input, which may be active high (a, c) or active low (b, d). When the enable input is asserted, the device behaves like an ordinary buffer or inverter. When the enable input is negated, the device output “floats”; that is, it goes to a highimpedance (Hi-Z), disconnected state and functionally behaves as if it weren’t even there. Buffer three-state Disponibles Comercialmente ICTP FPGA-VHDL

32 Bus de Tres Estados (Three States Bus)
Un bus de tres estados es creado al unir salidas tres estados de distintos CI El circuito de control de las habilitaciones de salidas (output enables) debe ser hecho de tal modo que al menos unos de los CIs tenga su salida habilitada Este CI habilitado podrá transmitir ‘1’ y ‘0’ en el bus ICTP FPGA-VHDL

33 Three States Comerciales
Independent enable inputs, as in the ’125 and ’126, are not necessary. Thus, to reduce the package size in wide-bus applications, most commonly used MSI parts contain multiple three-state buffers with common enable inputs. For example, Figure 5-56 shows the logic diagram and symbol for a 74x541 octal noninverting three-state buffer. Octal means that the part contains eight individual buffers. Both enable inputs, G1_L and G2_L, must be asserted to enable the device’s three-state outputs. The little rectangular symbols inside the buffer symbols indicate hysteresis, an electrical characteristic of the inputs that improves noise immunity, as we explained in Section The 74x541 inputs typically have 0.4 volts of hysteresis. ICTP FPGA-VHDL

34 Three States – Aplicación Principal
Figure 5-57 shows part of a microprocessor system with an 8-bit data bus, DB[0–7], and a 74x541 used as an input port. The microprocessor selects Input Port 1 by asserting INSEL1 and requests a read operation by asserting READ. The selected 74x541 responds by driving the microprocessor data bus with usersupplied input data. Other input ports may be selected when a different INSEL line is asserted along with READ. ICTP FPGA-VHDL

35 Bus Bidireccional ‘Z’ Octal Three-State Transceiver
A bus transceiver contains pairs of three-state buffers connected in opposite directions between each pair of pins, so that data can be transferred in either direction. For example, Figure 5-58 on the preceding page shows the logic diagram and symbol for a 74x245 octal three-state transceiver. The DIR input determines the direction of transfer, from A to B (DIR = 1) or from B to A (DIR = 0). The three-state buffer for the selected direction is enabled only if G_L is asserted. A bus transceiver is typically used between two bidirectional buses, as shown in Figure Three different modes of operation are possible, depending on the state of G_L and DIR, as shown in Table As usual, it is the designer’s responsibility to ensure that neither bus is ever driven simultaneously by two devices. However, independent transfers where both buses are driven at the same time may occur when the transceiver is disabled, as indicated in the last row of the table. Octal Three-State Transceiver ICTP FPGA-VHDL

36 Bus Three-State Bidireccional
(Transceiver) determines the direction of transfer, from A to B (DIR = 1) or from B to A (DIR = 0). The three-state buffer for the selected direction is enabled only if G_L is asserted. A bus transceiver is typically used between two bidirectional buses, as shown in Figure Three different modes of operation are possible, depending on the state of G_L and DIR, as shown in Table As usual, it is the designer’s responsibility to ensure that neither bus is ever driven simultaneously by two devices. However, independent transfers where both buses are driven at the same time may occur when the transceiver is disabled, as indicated in the last row of the table. ICTP FPGA-VHDL

37 Bus Bidireccionales - Ejemplos
As you have learned, in computers the microprocessor controls and communicates with the memories and the input/output (I/O) devices via the internal bus structure, as indicated in Figure 13–74. A bus is multiplexed so that any of the devices connected to it can either send or receive data to or from one of the other devices. A sending device is often called a master or source, and a receiving device is often called a servant or acceptor. At any given time, there is only one source active. For example, the RAM may be sending data to the input/ output (I/O) interface under control of the microprocessor. ICTP FPGA-VHDL

38 Bus Bidireccionales - Ejemplos
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39 Three State Representación Temporal
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40 Familias CMOS HC y HCT ICTP FPGA-VHDL

41 Comportamiento Dinámico de los CMOS
Velocidad Consumo de Potencia Tiempo de Transición Retardo de Propagación Potencia Estática Potencia Dinámica ICTP FPGA-VHDL

42 Velocidad – Tiempo de Transición
La cantidad de tiempo que toma una salida en cambiar de un estado a otro Ideal Real The amount of time that the output of a logic circuit takes to change from one state to another is called the transition time. Figure 3-36(a) shows how we might like outputs to change state—in zero time. However, real outputs cannot change instantaneously, because they need time to charge the stray capacitance of the wires and other components that they drive. A more realistic view of a circuit’s output is shown in (b). An output takes a certain time, called the rise time (tr), to change from LOW to HIGH, and a possibly different time, called the fall time (tf), to change from HIGH to LOW Even Figure 3-36(b) is not quite accurate, because the rate of change of the output voltage does not change instantaneously, either. Instead, the beginning and the end of a transition are smooth, as shown in (c). To avoid difficulties in defining the endpoints, rise and fall times are normally measured at the boundaries of the valid logic levels as indicated in the figure. With the convention in (c), the rise and fall times indicate how long an output voltage takes to pass through the “undefined” region between LOW and HIGH. The initial part of a transition is not included in the rise- or fall-time number. Instead, the initial part of a transition contributes to the “propagation delay” number discussed in the next subsection. Mediciones tr 0->1 tiempo de subida (rise time) tf t1->0 tiempo de bajada (fall time) ICTP FPGA-VHDL

43 Velocidad – Retardo de Propagación
Es la cantidad de tiempo que toma desde que cambia una entrada hasta que se produce un cambio en la salida tpHL: tiempo entre el cambio de una entrada y el correspondiente cambio en la salida cuando la salida cambia de ‘1’ a ‘0’ tpLH: tiempo entre el cambio de una entrada y el correspondiente cambio en la salida cuando la salida cambia de ‘0’ a ‘1’ ICTP FPGA-VHDL

44 Consumo de Potencia de un CMOS
Potencia Estática: cuando las salidas del CI CMOS no están cambiando. El consumo de potencia estática de un CMOS es sumamente bajo debido a la muy baja corriente necesaria para los CMOS Potencia Dinámica: cuando las salidas del CI CMOS están cambiando. El consumo de potencia dinámica depende de tres parámetros principalmente: Frecuencia de funcionamiento, tensión de alimentación, y capacitancia de la carga. La formula para calcular el consumo de potencia es la siguiente: ICTP FPGA-VHDL

45 Diferentes Familias Lógicas
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46 Encapsulados Disponibles
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47 Encapsulados Disponibles
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48 Evolución de los Transistores / CI
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49 Tamaño de un Transistor CMOS
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